For the design of digital circuits on the scale of VLSI (very large scale integration) technology, designers often employ computer aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aide in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
After writing and compiling HDL code, the design of an integrated circuit (IC) or a system which includes multiple integrated circuits must be verified to be correct. Verification is often the biggest bottle-neck for today's complex circuit designs, such as ASICs (Application Specific Integrated Circuits). Continually advancing processing technology, and the corresponding explosion in design size and complexity, have led to verification problems that are impossible or difficult to solve using traditional simulation tools. In addition, an increasing number of circuit applications that process large quantities of data (e.g. video display) in real time require verification techniques that run at near real time speeds. As a result, a growing number of ASIC designers are building boards (typically printed circuit boards) using multiple ICs known as field programmable gate arrays (FPGA) to verify their ASIC designs. Another advantage of building prototype boards with FPGAs is that it allows software development and debugging to happen in parallel with the design and debug of the final ASIC thereby reducing the development time of the product. However, ASIC designers face several challenges in prototyping and debugging the design using FPGAs. One of the biggest challenges is the capacity of even the largest FPGAs is much smaller than the size of a complex ASIC. This means that the designers must struggle to partition their design into multiple FPGAs, with few or no tools to help them make good partitioning decisions, and no way to model the characteristics during synthesis of partitioning. Thus, designers must iterate between an HDL synthesis process and partitioning of the board implementation which requires a considerable amount of time and tends to lengthen the product development time.
Two approaches are known in the prior art for creating/partitioning a design across multiple integrated circuits (ICs). One approach partitions a design after a completed synthesis from HDL code. This approach is shown in FIG. 1A. Another approach separately synthesizes the HDL codes that had been designed/written for separate integrated circuits; this is shown in FIG. 1B.
FIG. 1A shows a method 10 for partitioning a design across multiple ICs after HDL synthesis is completed. In operation 12 of this method, HDL code is prepared with no attempt at partitioning logic between multiple ICs. In operation 14, the HDL prepared in operation 12 is compiled to produce a netlist which is typically optimized by performing logic optimization. Thereafter, a mapping process maps the netlist to a specific target technology/architecture which is determined by the targeted architecture of the FPGA. It is well-known that the various vendors of FPGA ICs such as Xilinx and Altera, use different arrangements of transistors to create logic circuits. Accordingly, a technology independent netlist that is often created by the compilation of HDL code must be mapped to the specific technology in the vendor's IC which will be used to implement the logic. At the end of operation 14, the synthesis has been completed and a netlist which is specific to the technology/architecture used in the vendor's IC is now provided. This netlist is effectively at a gate level and is partitioned in operation 16 between/among several ICs. After operation 16 which partitions to create several ICs, a conventional place and route operation is performed on the logic circuit in operation 18 in order to create a design of the circuitry in each of the ICs.
An example of the approach shown in FIG. 1A is a logic emulation product System Realizer by Quickturn. Another example of this approach is provided by a software tool from Auspey of Cupertino, Calif. The quality of the resulting partitioning is poor, requiring either a large number of integrated circuits at low utilization on each IC or a substantial manual effort to guide the partitioning. This manual effort is difficult is because of a tremendous level of detail in the gate level netlist.
FIG. 1B shows another example in the prior art which is used to create separate ICs. This approach attempts to design the HDL source code, before HDL synthesis, into separate HDL designs which are connected by a netlist. In this method 20, operation 22 involves the preparation of HDL code for a first integrated circuit while operation 24 involves the preparation of HDL code for a second integrated circuit. Then a netlist in operation 26 is prepared (e.g., by preparing another HDL code) which will connect the two integrated circuits through a structure with connections, such as connections on a printed circuit board (PCB). Then in operation 28, synthesis is performed separately for each of the two integrated circuits. Thus, the first integrated circuit is synthesized by operations 30, 32, and 34, and the second integrated circuit is synthesized by operations 36, 38, and 40. While the quality of the resulting partition can be good from method 20, this method often requires substantial manual efforts in creating and changing the HDL code to reorganize design hierarchy such that two separate chips are synthesized from the two HDL files.
From the foregoing, it can be seen that HDL synthesis and partitioning are typically separate, disjoint steps in the process flow. Synthesis decisions are made without understanding how the design is to be partitioned across multiple ICs, such as FPGAs in the case of method 10, which results in prototypes that do not run at the desired speed. Further, partitioning decisions are made without any feedback about their impact on utilization and system performance. The result is that the designers must typically iterate several times between synthesis and partitioning. Each iteration is time consuming and extremely tedious, resulting in loss of productivity and increasing the time to develop a prototype. This process may also need to be repeated when the prototype has been exercised (tested) and changes are made to the original source code. Thus, it can be seen that it is desired to provide an improved method and apparatus for designing integrated circuits.